The present invention relates to computer systems and more particularly to stalling a processor pipeline upon register hazard detection.
Advanced processors employ pipelining techniques to execute instructions at very high speeds. On such processors, the overall machine is organized as multiple pipelines consisting of several cascaded stages of hardware. Instruction processing is divided into a sequence of operations, and each operation is performed by hardware in a corresponding pipeline stage (xe2x80x9cpipe stagexe2x80x9d or xe2x80x9cstagexe2x80x9d). Independent operations from several instructions may be processed simultaneously by different pipe stages, increasing the instruction throughput of the processor.
One challenge faced by processor designers is what to do when the execution of one instruction in a pipeline depends on the execution of one or more previously issued instructions. If data from a first instruction in a pipeline is needed by a second instruction in the pipeline, then the unavailability of the data from the first instruction causes a delay in the execution of the second instruction. In such a case, a portion of the pipeline may need to be halted, or stalled, until the first instruction completes execution so the resulting data can be used by the second instruction. This condition is called a hazard.
For example, consider the following set of instructions:
XOR R1, R2xe2x86x92R3
LOAD (R4)xe2x86x92R3
ADD R3, R5xe2x86x92R6
Proper calculation of result R6 requires that the operands of the ADD instruction, R3 and R5, be correct. For most processor architectures, this would require that R3 contain data resulting from execution of the LOAD instruction rather than execution of the XOR instruction. Unfortunately, the LOAD instruction may take longer to execute than the ADD instruction. Consequently, execution of the ADD instruction must be delayed by stalling the pipeline until the LOAD instruction is completed. This is known as a read after write (RAW) hazard because the ADD instruction must read register R3 after the LOAD instruction writes to register R3.
Hazard detection may be performed in parallel with the reading of the registers while an instruction is in the register read stage (also called the operand read stage) of the pipeline. Unfortunately, in high frequency processors, the hazard may not be detected until after the instruction has completed the register read stage and source data has been presented to the execute stage. For example, referring to the set of instructions presented above, upon detecting a hazard on register R3, the pipeline may be stalled after the ADD instruction has already been presented to the execute stage of the pipeline. Consequently, erroneous data is calculated for the ADD instruction using the result of the XOR instruction as the operand value for R3 rather than the result of the LOAD instruction. If this happens, the pipeline is typically flushed after the LOAD instruction is completed, and the instructions are re-executed beginning with the ADD instruction.
For one embodiment of the present invention, a hazard on a register is detected based on the register ID from a latch of a first stage of a processor pipeline. The pipeline is stalled after a stale value of the register is stored in a latch of a later stage of the pipeline. The stale value in the latch is then replaced with a fresh value while the pipeline is stalled.
Other features and advantages of the present invention will be apparent from the accompanying figures and the detailed description that follows.